Majid Al-RaimiCourse takeaways and getting started

COE 592Lecture 00Part 02

Course takeaways and getting started

What the course promises you will be able to do, the five pillars of efficient deep learning on constrained devices, and what to do in week one.

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Why this part matters

This part is the course contract. Every later lecture, from efficiency metrics through pruning, quantization, architecture search and deployment, is one turn of a five-step loop that slide 11 draws as a neural network funnelling down into a small development board.

Your exams and your research project will ask you to do two things with that loop: place a technique in it (is knowledge distillation an accelerate step or a compare step?), and compute whether a given model fits a given device. Both start here. The part also covers what the instructor asks of you in week one, and what the deck deliberately leaves to Blackboard.

By the end you can

  1. State the five course takeaways and reorder them as a measure, optimize, compare, explore, deploy loop.
  2. Compute a model's weight size from parameter count and bit width, and judge whether it fits a device tier.
  3. Explain why accuracy alone cannot select a model for a constrained device.
  4. Distinguish on-device inference from on-device training by their memory needs.
  5. Set up a week-one plan: survey, prerequisites check, device tier, candidate model, metrics log.

On the first evening each student says three things out loud: their name, their educational background (previous studies), and their work background (current or previous work, industry or occupation). Then everyone opens the Pre-course survey at https://forms.cloud.microsoft/r/5ssu8gkcS9, also printed as a QR code on slide 10, and answers questions about background, skills and expectations.

It is tempting to file both under administration, but they serve the same purpose as takeaway 1 later in this part: you cannot tune what you have not measured. A graduate course on efficient deep learning draws people from computer engineering, electrical engineering, computer science and industry. Some have trained convolutional networks for years and never flashed a microcontroller; others write firmware for embedded systems daily and have never opened PyTorch. The instructor uses the room's answers to set depth and pacing, so an honest answer about a gap is worth more to you than an impressive one.

What is worth refreshing before week two

The deck does not list prerequisites, so treat the following as a hedged suggestion drawn from what the course will ask you to do rather than as a slide claim. The topics ahead (compression, pruning, quantization, deployment to boards) match the syllabus of MIT's 6.5940 TinyML and Efficient Deep Learning Computing, which lists an introductory machine learning subject and a computation structures subject as its prerequisites. Translated to tools, four skills will carry most of the weight.

Skills that will probably matter, and why

Python
Every framework, script and notebook in efficient deep learning assumes it. The PyTorch beginner tutorial itself assumes basic familiarity with Python.
PyTorch
The compression and quantization literature (Deep Compression, MCUNet, TinyTL) ships PyTorch code; you will read and modify such code, not write frameworks.
Basic CNNs
Convolutions, pooling and fully connected layers are what get pruned and quantized. The free Deep Learning book by Goodfellow, Bengio and Courville covers them.
C for microcontrollers
LiteRT for Microcontrollers is written in C++ 17 for 32-bit platforms with no operating system, so deploying to a board means touching C or C++ code.

None of these needs to be deep on day one. If you can train a small classifier in PyTorch, explain what a convolution computes, and compile and flash a blinking-LED program in C, you can follow the first weeks and fill in the rest as the loop demands it.

Recall

What three things does the icebreaker ask each student to share?

Name, educational background (previous studies), and work background (current or previous work, industry or occupation).

Take a small image classifier with 3 million parameters, trained in PyTorch and saved in 32-bit floating point. Its weights alone occupy 12 MB. A Raspberry Pi Pico has 2 MB of flash and 264 KB of SRAM. The model does not fit, and no amount of accuracy changes that. Everything this course teaches is what you do next.

Slide 11 states the promise as five takeaways. You will know the key Efficiency metrics for deep learning computing. You will understand how to speed up Inference and Training of neural networks on resource-constrained platforms. You will analyse the tradeoffs between different optimization techniques. You will be aware of recent research trends and industry practice. And you will get hands-on experience compressing and implementing deep learning models on resource-constrained devices. The infographic relabels the same five as Measure efficiency, Accelerate, Analyse trade-offs, Track the frontier, and Build and deploy, with a five-word footer: Measure, Optimize, Compare, Explore, Deploy.

A network funnels into one spine; the five pillars light up in order, the board at the bottom powers on, and a loop returns to pillar 1

Read the five as a loop, not a list

The order on the slide is not arbitrary. It is the order in which you actually work. You measure a baseline: size, memory, compute, latency, energy. You apply one optimization, say pruning. You compare the new numbers against the baseline and note what the step cost in accuracy. You look to the research literature and to industry for the next technique. You deploy on the real board to check that the paper numbers survive contact with hardware, because measured latency and energy routinely differ from analytical estimates. Then you measure again, and the loop turns.

PillarVerbQuestion you askDeep Compression example
1 Measure efficiencyMeasureHow big, how slow, how hungry is the baseline?AlexNet: 240 MB, 61 M parameters, 32-bit weights
2 AccelerateOptimizeWhich technique shrinks the cost that hurts most?Prune 9x fewer connections, quantize to 5 bits, Huffman code
3 Analyse trade-offsCompareWhat did each step cost in accuracy or effort?35x smaller with no accuracy loss, after retraining
4 Track the frontierExploreWhat has research or industry done since?MCUNet, TinyTL and on-device training under 256 KB
5 Build and deployDeployDoes it really run on the target hardware?3x to 4x layerwise speedup and 3x to 7x energy efficiency measured on hardware
The five pillars as one loop, with Deep Compression (Han, Mao and Dally, 2016) as the running example

Deep Compression is the canonical worked loop. Han, Mao and Dally started from AlexNet at 240 MB and VGG-16 at 552 MB (measure), pruned redundant connections, quantized the survivors from 32 to as few as 5 bits and Huffman coded the result (optimize), reported 35x and 49x reductions with no loss of accuracy (compare), and measured 3x to 4x layerwise speedup and 3x to 7x better energy efficiency on real hardware (deploy). The companion paper on learning both weights and connections had already shown pruning alone cutting AlexNet from 61 M to 6.7 M parameters. Everything after 2016 (MCUNet, TinyTL, on-device training under 256 KB) is the explore step feeding the next turn.

A preview of the efficiency metrics

Slide 11 names the metrics without listing them; the list below previews later lectures and is not slide content. The ordering follows the MIT 6.5940 sequence, which opens with the basics of efficient deep learning before pruning, quantization, neural architecture search, distillation and on-device training. Learn the names now so the loop has something concrete to measure.

MetricWhat it countsTypical unit
Parameter countHow many learnable weights and biases the model hasmillions (M)
Model sizeBytes needed to store the weights: parameters times bits per weight over 8MB or KB
Peak memoryThe most memory needed at any moment: weights plus the largest activation tensorsMB or KB
ComputeMultiply-accumulate operations (MACs) or floating-point operations (FLOPs) per inferenceMMACs or GFLOPs
LatencyTime from one input to its outputms
ThroughputInferences completed per secondinferences/s
EnergyJoules per inference, or average power while runningmJ or mW
Efficiency metrics you will meet (preview, not slide content)

The first two are the easiest to compute by hand, and the calculation is one you will repeat all term. A weight stored in b bits takes b / 8 bytes, so the size of the weights is the parameter count times bits per weight divided by eight.

size (bytes)=Nparams×b8\text{size (bytes)} = \frac{N_{\text{params}} \times b}{8}
Weight storage for N parameters at b bits each; MB here means one million bytes

Worked example

A 3 million parameter model at four bit widths

  1. Start from float32

    3,000,000 × 32 / 8 = 12,000,000 bytes, about 12 MB. This is what PyTorch saves by default.
  2. Halve the bits, halve the bytes

    At 16 bits the same weights take 6 MB; at 8 bits, 3 MB; at 4 bits, 1.5 MB. Nothing else changed: the parameter count is identical.
  3. Test against two boards

    The Raspberry Pi Pico has 2 MB of flash, so only the 4-bit version fits. The Arduino Nano 33 BLE Sense Rev2 has 1 MB, so none of the four fit, and quantization alone is not enough.
  4. Result

    Bit width divides size, but the target device decides whether the result is small enough. Below 1 MB this model also needs pruning or a different architecture.
Bits per weightCalculationSizeFits Pico flash (2 MB)?Fits Nano 33 BLE Sense flash (1 MB)?
32-bit3,000,000 × 32 / 812,000,000 B (12 MB)NoNo
16-bit3,000,000 × 16 / 86,000,000 B (6 MB)NoNo
8-bit3,000,000 × 8 / 83,000,000 B (3 MB)NoNo
4-bit3,000,000 × 4 / 81,500,000 B (1.5 MB)YesNo
3 M parameters at four bit widths, tested against two microcontroller flash budgets
The same 3 M parameters at 32, 16, 8 and 4 bits; only the 4-bit bar slides inside the 2 MB flash line

Try it yourself. The calculator applies the formula for any parameter count and bit width and checks the result against generic device tiers. The device figures are datasheet capacities for one example board per tier (Arduino, Raspberry Pi and NVIDIA product pages), not what is free once the runtime and your code are loaded.

SimulatorDoes it fit?
Target device

Microcontroller, example board: Arduino Nano 33 BLE Sense Rev2 (nRF52840)

3.00 M
Bits per weight
100 KB
Weight size12.00 MB3.00 M × 32 ÷ 8
Activations100 KByour estimate, not computed
Flash, weights storedDoes not fit
needs 12.00 MB (weights only)of 1.05 MB
SRAM, weights read from flashFits
needs 116 KB (activations plus a 16 KB allowance for runtime and stack)of 262 KB
SRAM, weights copied inDoes not fit
needs 12.12 MB (weights, activations and the same allowance)of 262 KB

Activations, the runtime and your application code also need memory. These figures are datasheet capacities, not what is free. Model sizes use MB as 10^6 bytes; the microcontroller banks use the datasheet binary figures (1 MiB flash, 256 KiB SRAM), which are slightly larger.

Three misconceptions the loop corrects

Inference stacks weights and one set of activations; training adds stored activations, gradients and optimizer state and spills past the SRAM line

Quick check

You compare pruning and quantization on the same network and report size, latency and accuracy for each. Which takeaway is this?

Quick check

A network has 12 million parameters stored as 8-bit integers. What is its weight size?

Quick check

Why can accuracy alone not choose a model for a microcontroller?

Quick check

Which memory cost appears in on-device training but not in on-device inference?

Recall

Name the five course takeaways in the order of the loop, then say what comes after the fifth.

Measure efficiency, accelerate (optimize), analyse trade-offs (compare), track the frontier (explore), build and deploy. After deploying you measure the deployed model again, and the loop turns.

Recall

A 3 M parameter model with 8-bit weights: how many bytes, and does it fit 1 MB of flash?

3,000,000 × 8 / 8 = 3,000,000 bytes, about 3 MB. It does not fit 1 MB of flash; even at 4 bits it is 1.5 MB.

Recall

Why is on-device training harder than on-device inference?

Training must store activations for the backward pass, gradients and optimizer state, so peak memory is far higher. TinyTL shows activations, not parameters, are the bottleneck, and LiteRT for Microcontrollers does not support on-device training.

Slide 12 contains three words: "View on Blackboard". That is the whole syllabus section of the deck. It does not give grading weights, exam dates, project deliverables, a textbook, an office location or office hours. Anything you read elsewhere claiming to know those for this course is not coming from these slides.

What is known so far (meeting details from the course registry, not this deck)

Meetings
Monday and Wednesday, 20:10 to 21:25
Room
Building 59, Room 2004
Syllabus, grading, deliverables
On Blackboard, not in this deck
Textbook, office, office hours
Not stated in this deck; check Blackboard

Plan the project before the syllabus tells you to

Takeaway 5 promises hands-on experience compressing and implementing models on constrained devices, and the MIT counterpart of this course ends in an open-ended design project. Read that as a strong hint that a hardware Deployment is coming, whatever Blackboard eventually calls it. The students who struggle with such projects are rarely short of techniques; they are short of a baseline to compare against and a board that arrives on time. Both are fixed in week one.

  1. Pick a device tier first. The memory budget of the tier decides which models are even candidates, so the device is an input to model selection, not an output of it.
  2. Pick a candidate model that already fits, or is within one or two optimizations of fitting, and record its parameter count and float32 size with the formula from the previous concept.
  3. Start a metrics log before the first optimization. A baseline recorded after you have started changing things is not a baseline.
TierExample boardMemoryWhat it is typically asked to run
MicrocontrollerArduino Nano 33 BLE Sense Rev2 (nRF52840)1 MB flash, 256 KB SRAMKeyword spotting, gesture and anomaly detection, tiny image classifiers
MicrocontrollerRaspberry Pi Pico and Pico 22 MB flash and 264 KB SRAM; Pico 2 has 4 MB and 520 KBSame class, a little more headroom
Single-board computerRaspberry Pi 4 Model B1 to 8 GB LPDDR4 RAMQuantized MobileNet-class vision, small detectors, a Linux runtime
GPU moduleJetson Orin Nano Super Developer Kit8 GB LPDDR5 at 102 GB/s, 67 INT8 TOPSReal-time detection, small transformers, on-device fine-tuning
One example board per tier, with datasheet capacities (Arduino, Raspberry Pi and NVIDIA product pages)

The last column is a guide, not a datasheet claim. MCUNet reached over 70% ImageNet top-1 accuracy on a commercial microcontroller, so the microcontroller tier is more capable than its numbers suggest, but only after the whole loop has been applied to a purpose-built architecture. A model chosen for a GPU module and then squeezed onto a microcontroller is the hardest path in the course.

WhenWhat to record
Week 1Target device tier and its flash, SRAM or RAM budget from the datasheet
Week 1Candidate model, its parameter count and float32 weight size
Week 1Baseline accuracy on a held-out set you will not change later
First run on hardwareLatency per inference and peak memory as the runtime reports them
Every optimizationThe same four numbers again, next to the baseline, plus what it cost
A starter metrics log

Keep the log as a plain table with one row per experiment and the same columns every time: accuracy, parameter count, size, peak memory, latency, energy if you can measure it, and a one-line note of what changed. This is the compare step made permanent, and it is the table an examiner or a reviewer will want to see.

Quick check

Where is the COE 592 grading scheme published, according to the deck?

Recall

Why does the deck not tell you the grading scheme, and what should you do about it?

Slide 12 says only "View on Blackboard". The syllabus, assessments, textbook and office hours live on Blackboard, so check there; the site will add assessments once the syllabus is transcribed.

Recall

What three numbers should be in your metrics log before you run the first optimization?

Baseline accuracy, weight size (from parameter count and bit width) and latency on the target hardware, with peak memory as soon as the runtime reports it.

Recap

If you remember nothing else

  • Introduce yourself with name, education and work background, and fill in the pre-course survey so the course can be calibrated to the room.
  • Five takeaways: measure efficiency, accelerate, analyse trade-offs, track the frontier, build and deploy. Read them as a loop, not a list.
  • Weight size in bytes equals parameters times bits per weight divided by 8: 3 M parameters is 12 MB at 32-bit and 1.5 MB at 4-bit.
  • Size, peak memory, compute, latency, throughput and energy are separate metrics and can disagree.
  • Compression trades accuracy and effort; Deep Compression's 35x came with retraining, not for free.
  • Training on device must hold activations and gradients, far more than inference, and LiteRT for Microcontrollers does not support it.
  • The syllabus, grading and deliverables are on Blackboard, not in this deck. Class: Mon and Wed 20:10 to 21:25, Building 59, Room 2004.
  • Pick a device tier and a candidate model in week one, and start a metrics log before the first optimization.

Sources